A memory device in an electronic system is used for storing various types of data. The data often need to be transmitted to a data processing device in the system, e.g., a central processing unit (CPU) or a programmable logic device (PLD), through a set of communication channels and processed therein to produce certain results. A set of communication channels typically includes one or more channels carrying data signals (DQ) and one channel carrying a data strobe signal (DQS), whose rising/falling edges are used by a device, e.g., a memory controller, that interfaces the memory device with the data processing device to sample the DQ signals.
A DQS signal coming out of a memory device is usually configured to be edge-aligned with its associated DQ signals so that there is no phase shift between the two types of signals when they reach the memory controller. In practice, to sample the DQ signals accurately, it is preferred that there be a phase delay, e.g., 90° or 72°, between the DQ signals and the DQS signal so that a data sampling edge of the DQS signal is positioned within a data sampling window associated with the DQ signals. Preferably, the DQS signal is at the center of the data sampling window.
The size of a data sampling window depends upon which data sampling scheme is chosen for a memory device. FIGS. 1A and 1B schematically illustrate two typical data sampling schemes that are often used by a memory controller: (1) the single-data-rate (SDR) scheme in FIG. 1A in which a DQ signal 160 is sampled once per cycle of DQS signal 120; and (2) the double-data-rate (DDR) scheme in FIG. 1B in which a DQ signal 170 is sampled twice per cycle of DQS signal 130, once on the rising edge of the DQS signal and once on the falling edge. In both schemes, the DQS signals (120, 130) are initially edge-aligned with their respective DQ signals (160, 170). But a single data bit of the DQ signal 160 is twice as long as a single data bit of the DQ signal 170.
In the SDR scenario, only the rising edges of a 180°-delayed DQS signal 140 are used for sampling the DQ signal 160. By contrast, both the rising and falling edges of a 90°-delayed DQS signal 150 are used for sampling the DQ signal 170 in the DDR scenario. As a result, the data sampling window W90 in FIG. 1B is only about half the data sampling window W180 in FIG. 1A. Clearly, a small data sampling window increases the possibility of data sampling errors and therefore compromises efforts toward improving a memory device's performance by increasing its operating frequency.
Meanwhile, there are many factors, e.g., process, voltage and temperature (PVT), etc., that can change the phase shift between a DQ signal and a DQS signal. Even if a DQS signal is initially center-aligned with a DQ signal, it may subsequently “drift” away from the center of the data sampling window if the environment varies.
In view of the above discussion, it is desirable to develop a memory interface circuit architecture that adaptively determines a desired phase delay to center-align a DQS signal to a DQ signal and dynamically adjusts the phase-shifted DQS signal when its sampling edge deviates from the center of the DQ signal's data sampling window.